How to display bold characters?

| Monday, August 24, 2009


Using following program bold characters can be displayed. Note that this program takes help of UNIX facilities. This may not work on PC based simulators.

module bold;

initial begin

$display ("Normal Text");
$display ("\033[1mBold Text");
$display ("\033[mSwitch back to Normal Text.....");
$display ("\033[7mInverse Text.");
$display ("\033[mSwitch back to Normal Text.....");

$display ("\033[1mBold Text \033[mfollowed by \033[7mInverse text \033[m");
end

endmodule

Sample Verilog Questions asked in Interviews. Please contribute with your questions. If you are looking for answers please refer to website Site FAQ

../images/main/bullet_4dots_green.gif Differentiate between Inter assignment Delay and Inertial Delay.

../images/main/bullet_4dots_green.gif What are the different State machine Styles ? Which is better ? Explain disadvantages and advantages.

../images/main/bullet_4dots_green.gif What is the difference between the following lines of code ?

  • reg1<= #10 reg2 ;
  • reg3 = # 10 reg4 ;

../images/main/bullet_4dots_green.gif What is the value of Var1 after the following assignment ?

reg Var1;

initial begin

Var1<= "-"

end

../images/main/bullet_4dots_green.gif In the below code, Assume that this statement models a flop with async reset. In this, how does the synthesis tool, figure out which is clock and which is reset. Is the statements within the always block is necessary to find out this or not ?

 
  1 module which_clock (x,y,q,d);
  2 input x,y,d;
  3 output q;
  4 reg q;
  5 
  6 always @ (posedge x or posedge y)
  7    if (x) 
  8      q <= 1'b0;
  9    else
 10      q <= d;
 11 
 12 endmodule

../images/main/bullet_4dots_green.gif What is the output of the two codes below ?

 
  1 module quest_for_out();
  2 
  3 integer i;
  4 reg clk;
  5 
  6 initial begin
  7   clk = 0;
  8    #4  $finish;
  9 end
 10 
 11 always  #1  clk =  ! clk;
 12 
 13 always @ (posedge clk)
 14 begin : FOR_OUT
 15   for (i=0; i < i =" i">
 16     if (i == 5) begin
 17       disable FOR_OUT;
 18     end
 19     $display ("Current i : ‰g",i);
 20   end
 21 end
 22 endmodule
 
  1 module quest_for_in();
  2 
  3 integer i;
  4 reg clk;
  5 
  6 initial begin
  7   clk = 0;
  8    #4  $finish;
  9 end
 10 
 11 always  #1  clk =  ! clk;
 12 
 13 always @ (posedge clk)
 14 begin
 15   for (i=0; i < i =" i">
 16     if (i == 5) begin
 17       disable FOR_IN;
 18     end
 19     $display ("Current i : ‰g",i);
 20   end
 21 end
 22 endmodule

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