How to model Transport and Inertial Delays in Verilog?

Following simple example can illustrate the concept.

module delay(in,transport,inertial);
input in;
output transport;
output inertial;

reg transport;
wire inertial;

// behaviour of delays
always @(in)
begin
transport <= #10 in;
end

assign #10 inertial = in;

endmodule // delay

The timing Diagram for input and outputs
_______ __
in _____| |_____||_______

_______ __
transport _________| |_____||_____

_______
inertial _________| |____________

Non blocking assignment gives you transport delay. Whenever input changes, output is immediately evaluated and kept in a event queue and assigned to output after specified "transport" delay.

In Continuous assign statement the latest event overrides the earlier event in the queue.

I am attaching rudimentary testbench and its output. Hope this helps.

module test;
reg in;
wire transport, inertial;

// instantiate delay module
delay my_delay(in,transport,inertial);

// apply inputs
initial
begin
in = 0;
#20 in = 1;
#20 in = 0;
#30 in = 1;
#5 in = 0;
#30 in = 1;
#30 $finish;
end
// monitor signals
initial
begin
$monitor($time," in = %b transport = %b inertial = %b",
in,transport, inertial);
end

endmodule // test

log file
Compiling source file "delay.v"
Highest level modules:
test

0 in = 0 transport = x inertial = x
10 in = 0 transport = 0 inertial = 0
20 in = 1 transport = 0 inertial = 0
30 in = 1 transport = 1 inertial = 1
40 in = 0 transport = 1 inertial = 1
50 in = 0 transport = 0 inertial = 0
70 in = 1 transport = 0 inertial = 0
75 in = 0 transport = 0 inertial = 0
80 in = 0 transport = 1 inertial = 0
85 in = 0 transport = 0 inertial = 0
105 in = 1 transport = 0 inertial = 0
115 in = 1 transport = 1 inertial = 1
L35 "delay.v": $finish at simulation time 135
81 simulation events

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