| Saturday, August 22, 2009
How does this xyz code get synthesized ?
Well it is a long story; let me cover that in the synthesis part of Verilog tutorial. You can refer to Actel HDL coding Style. One simple logic is: any code inside always blocks with edge sensitive sensitivity list, results in flip-flops and assign; inside level sensitive always blocks results in combo logic.
How do I implement Memories in Verilog ?
You can implement them by declaring 2-dimension arrays. More details can be found in the Verilog tutorial section "Modeling memories and FSM".
How do I read and write from a file ?
To Read from a file we use \$readmemh, where h stands for hex decimal. For writing we use \$writememh, \$fdisplay, \$fmonitor. You could refer to the Verilog tutorial section for more details.
What is this `timescale compiler directive ?
`timescale is used for specifying the reference time unit for the simulator. Syntax of the `timescale is as below:
`timescale /
example : `timescale 10ns/1ns
Timescale directive tends to make more sense at gatelevel simulation than at RTL simulation.
Can we mix blocking and nonblocking in one always block ?
Yes, we can have both blocking and nonblocking code in same always block. Some things that one should know to use this are:
• Blocking assignments are treated as combinational logic.
• One should not assign a variable in the same always block with both blocking and nonblocking assignments.
• Not all synthesis tools support this. (Design compiler supports this).

What is the output of AND gate in the circuit below, when A and B are as in waveform? Tp is the gate delay of respective gate.

Identify the circuit below, and its limitation.

What is the current through the resistor R1 (Ic) ?

Referring to the diagram below, briefly explain what will happen if the propagation delay of the clock signal in path B is much too high compared to path A. How do we solve this problem if the propagation delay in path B can not be reduced ?

What is the function of a D flip-flop, whose inverted output is connected to its input ?

Design a circuit to divide input frequency by 2.

Design a divide-by-3 sequential circuit with 50% duty cycle.

Design a divide-by-5 sequential circuit with 50% duty cycle.

What are the different types of adder implementations ?

Draw a Transmission Gate-based D-Latch.

Give the truth table for a Half Adder. Give a gate level implementation of it.

What is the purpose of the buffer in the circuit below, is it necessary/redundant to have a buffer ?

What is the output of the circuit below, assuming that value of 'X' is not known ?

Consider a circular disk as shown in the figure below with two sensors mounted X, Y and a blue shade painted on the disk for an angle of 45 degree. Design a circuit with minimum number of gates to detect the direction of rotation.

Design an OR gate from 2:1 MUX.

Design an XOR gate from 2:1 MUX and a NOT gate

What is the difference between a LATCH and a FLIP-FLOP ?

• Latch is a level sensitive device while flip-flop is an edge sensitive device.
• Latch is sensitive to glitches on enable pin, whereas flip-flop is immune to glitches.
• Latches take less gates (also less power) to implement than flip-flops.
• Latches are faster than flip-flops.

Design a D Flip-Flop from two latches.

Design a 2 bit counter using D Flip-Flop.

What are the two types of delays in any digital system ?

Design a Transparent Latch using a 2:1 Mux.

Design a 4:1 Mux using 2:1 Muxes and some combo logic.

What is metastable state ? How does it occur ?

What is metastability ?

Design a 3:8 decoder

Design a FSM to detect sequence "101" in input sequence.

Convert NAND gate into Inverter, in two different ways.

Design a D and T flip flop using 2:1 mux; use of other components not allowed, just the mux.

Design a divide by two counter using D-Latch.

Design D Latch from SR flip-flop.

Define Clock Skew , Negative Clock Skew, Positive Clock Skew.

What is Race Condition ?

Design a 4 bit Gray Counter.

Design 4-bit Synchronous counter, Asynchronous counter.

Design a 16 byte Asynchronous FIFO.

What is the difference between an EEPROM and a FLASH ?

What is the difference between a NAND-based Flash and a NOR-based Flash ?

You are given a 100 MHz clock. Design a 33.3 MHz clock with and without 50% duty cycle.

Design a Read on Reset System ?

Which one is superior: Asynchronous Reset or Synchronous Reset ? Explain.

Design a State machine for Traffic Control at a Four point Junction.

What are FIFO's? Can you draw the block diagram of FIFO? Could you modify it to make it asynchronous FIFO ?
How can you generate random sequences in digital circuits?

Q: What is the difference between a Verilog task and a Verilog function?
A:The following rules distinguish tasks from functions:

• A function shall execute in one simulation time unit;
a task can contain time-controlling statements.

• A function cannot enable a task;

• A function shall have at least one input type argument
and shall not have an output or inout type argument;
a task can have zero or more arguments of any type.

• A function shall return a single value;
a task shall not return a value.

________________________________________
Q: Given the following Verilog code, what value of "a" is displayed?
always @(clk) begin
a = 0;
a <= 1;
\$display(a);
end

A: This is a tricky one! Verilog scheduling semantics basically imply a
four-level deep queue for the current simulation time:

1: Active Events (blocking statements)
2: Inactive Events (#0 delays, etc)
4: Monitor Events (\$display, \$monitor, etc).

Since the "a = 0" is an active event, it is scheduled into the 1st "queue".
The "a <= 1" is a non-blocking event, so it's placed into the 3rd queue.
Finally, the display statement is placed into the 4th queue.

Only events in the active queue are completed this sim cycle, so the "a = 0"
happens, and then the display shows a = 0. If we were to look at the value of
a in the next sim cycle, it would show 1.

________________________________________
Q: Given the following snipet of Verilog code,
draw out the waveforms for clk and a
always @(clk) begin
a = 0;
#5 a = 1;
end

A:

10 30 50 70 90 110 130
___ ___ ___ ___ ___ ___ ___
clk ___| |___| |___| |___| |___| |___| |___| |___

a ___________________________________________________________

This obviously is not what we wanted, so to get closer, you could use
"always @ (posedge clk)" instead, and you'd get

10 30 50 70 90 110 130
___ ___ ___ ___ ___ ___ ___
clk ___| |___| |___| |___| |___| |___| |___| |___

___ ___
a _______________________| |___________________| |_______

________________________________________
Q: What is the difference between the following two lines of Verilog code?
#5 a = b;
a = #5 b;

A:
#5 a = b; Wait five time units before doing the action for "a = b;".
The value assigned to a will be the value of b 5 time units hence.

a = #5 b; The value of b is calculated and stored in an internal temp register.
After five time units, assign this stored value to a.

________________________________________
Q: What is the difference between:

c = foo ? a : b;

and

if (foo) c = a;
else c = b;

A:

The ? merges answers if the condition is "x", so for instance if foo = 1'bx, a = 'b10, and b = 'b11,
you'd get c = 'b1x.

On the other hand, if treats Xs or Zs as FALSE, so you'd always get c = b.

(Back)

________________________________________
Q: Using the given, draw the waveforms for the following
versions of a (each version is separate, i.e. not in the same run):
reg clk;
reg a;

always #10 clk = ~clk;

(1) always @(clk) a = #5 clk;
(2) always @(clk) a = #10 clk;
(3) always @(clk) a = #15 clk;

Now, change a to wire, and draw for:

(4) assign #5 a = clk;
(5) assign #10 a = clk;
(6) assign #15 a = clk;

A:

10 30 50 70 90 110 130
___ ___ ___ ___ ___ ___ ___
clk ___| |___| |___| |___| |___| |___| |___| |___

___ ___ ___ ___ ___ ___ ___
(1)a ____| |___| |___| |___| |___| |___| |___| |_

___ ___ ___ ___ ___ ___ ___
(2)a ______| |___| |___| |___| |___| |___| |___|

(3)a __________________________________________________________

Since the #delay cancels future events when it activates, any delay
over the actual 1/2 period time of the clk flatlines...

With changing a to a wire and using assign, we
just accomplish the same thing...

10 30 50 70 90 110 130
___ ___ ___ ___ ___ ___ ___
clk ___| |___| |___| |___| |___| |___| |___| |___

___ ___ ___ ___ ___ ___ ___
(4)a ____| |___| |___| |___| |___| |___| |___| |_

___ ___ ___ ___ ___ ___ ___
(5)a ______| |___| |___| |___| |___| |___| |___|

(6)a __________________________________________________________

________________________________________
Q: What is the difference between a Vera task and a Verilog task?
A:
________________________________________
Q: What is the difference between running the following snipet of code
on Verilog vs Vera?
fork {
#10;
}

cnt = 0;
for (i = 0; i < 50; i++) {
cnt++;
}
}

A:

(Back)

________________________________________

Q: Given \$a = "5,-3,7,0,-5,12";
Write a program to find the lowest number in the string.
A:
// BEGIN PERL SNIPET

\$a = "5,-5,-1,0,12,-3";
(@temp) = split (/,/, \$a);
\$lowest = \$temp[0];

for (\$i=0; \$i<6; \$i++) {
if (\$temp[\$i] < \$lowest) { \$lowest = \$temp[\$i]; }
}

print "Lowest value found was: \$lowest\n";

// END PERL SNIPET

NOTE: You could also replace the for loop with this:

foreach \$value (@temp) {
if (\$value < \$lowest) { \$lowest = \$value; }
}

________________________________________
Q: Write the code to sort an array of integers.
A:
/* BEGIN C SNIPET */

void bubblesort (int x[], int lim) {
int i, j, temp;

for (i = 0; i < lim; i++) {
for (j = 0; j < lim-1-i; j++) {

if (x[j] > x[j+1]) {
temp = x[j];
x[j] = x[j+1];
x[j+1] = temp;

} /* end if */
} /* end for j */
} /* end for i */
} /* end bubblesort */

/* END C SNIPET */

Some optimizations that can be made are that a single-element array does
not need to be sorted; therefore, the "for i" loop only needs to go from
0 to lim-1. Next, if at some point during the iterations, we go through
the entire array WITHOUT performing a swap, the complete array has been
sorted, and we do not need to continue. We can watch for this by adding
a variable to keep track of whether we have performed a swap on this
iteration.

________________________________________
Q: Write the code for finding the factorial of a passed integer.
Use a recursive subroutine.
A:
// BEGIN PERL SNIPET

sub factorial {
my \$y = shift;
if ( \$y > 1 ) {
return \$y * &factorial( \$y - 1 );
} else {
return 1;
}
}

// END PERL SNIPET

________________________________________
Q: In C, explain the difference between the & operator and
the * operator.
A:
& is the address operator, and it creates pointer values.
* is the indirection operator, and it dereferences pointers
to access the object pointed to.

Example:
In the following example, the pointer ip is assigned the
address of variable i (&i). After that assignment,
the expression *ip refers to the same object denoted by i:

int i, j, *ip;
ip = &i;
i = 22;
j = *ip; /* j now has the value 22 */
*ip = 17; /* i now has the value 17 */

________________________________________
Q: Write a function to determine whether a string is a palindrome (same
forward as reverse, such as "radar" or "mom").
A:
/* BEGIN C SNIPET */

#include

void is_palindrome ( char *in_str ) {
char *tmp_str;
int i, length;

length = strlen ( *in_str );
for ( i = 0; i < length; i++ ) {
*tmp_str[length-i-1] = *in_str[i];
}
if ( 0 == strcmp ( *tmp_str, *in_str ) ) printf ("String is a palindrome");
else printf ("String is not a palindrome");
}

/* END C SNIPET */

________________________________________
Q: Write a function to output a diamond shape according to the given (odd) input.
Examples: Input is 5 Input is 7
* *
*** ***
***** *****
*** *******
* *****
***
*
A:
### BEGIN PERL SNIPET ###

for (\$i = 1; \$i <= ((\$input * 2) - 1); \$i += 2) {
if (\$i <= \$input) {
\$stars = \$i;
\$spaces = (\$input - \$stars) / 2;
while (\$spaces--) { print " "; }
while (\$stars--) { print "*"; }
} else {
\$spaces = (\$i - \$input) / 2;
\$stars = \$input - (\$spaces * 2);
while (\$spaces--) { print " "; }
while (\$stars--) { print "*"; }
}
print "\n";
}
### END PERL SNIPET ###

________________________________________
Q: Given the following FIFO and rules, how deep does the FIFO need to be to
prevent underflowing or overflowing?

RULES:
1) frequency(clk_A) = frequency(clk_B) / 4
2) period(en_B) = period(clk_A) * 100
3) duty_cycle(en_B) = 25%
A:
Assume clk_B = 100MHz (10ns)

From (1), clk_A = 25MHz (40ns)

From (2), period(en_B) = 40ns * 100 = 4000ns, but we only output for 1000ns,
due to (3), so 3000ns of the enable we are doing no output work.

Therefore, FIFO size = 3000ns/40ns = 75 entries.

________________________________________
Q: Draw the state diagram to output a "1" for one cycle
if the sequence "0110" shows up (the leading 0s cannot be
used in more than one sequence).
A:

________________________________________
Q: Explain the differences between "Direct Mapped", "Fully Associative",
and "Set Associative" caches.
A:
If each block has only one place it can appear in the cache, the cache
is said to be direct mapped. The mapping is usually (block-frame address)
modulo (number of blocks in cache).

If a block can be placed anywhere in the cache, the cache is said to be
fully associative.

If a block can be placed in a restricted set of places in the cache, the cache
is said to be set associative. A set is a group of two or more
blocks in the cache. A block is first mapped onto a set, and then the block
can be placed anywhere within the set. The set is usually chosen by bit
selection; that is, (block-frame address) modulo (number of sets in cache).
If there are n blocks in a set, the cache placement is
called n-way set associative.
________________________________________
Q: Design a four-input NAND gate using only two-input NAND gates.
A:
Basically, you can tie the inputs of a NAND gate together to get an inverter, so...

(Back)

________________________________________
Q: Draw the state diagram for a circuit that outputs a "1" if the aggregate serial
binary input is divisible by 5. For instance, if the input stream is 1, 0, 1, we
output a "1" (since 101 is 5). If we then get a "0", the aggregate total is 10, so
we output another "1" (and so on).
A:
We don't need to keep track of the entire string of numbers - if something
is divisible by 5, it doesn't matter if it's 250 or 0, so we can just reset to 0.
So we really only need to keep track of "0" through "4".

5) What is delta simulation time?

10) Variable and signal which will be Updated first?

Signals

11)
12) In a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk? if yes, why?

Yes in a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk other wise it will result in pre and post synthesis mismatch.

13) Tell me
14) 15) What are different styles of Verilog coding I mean gate-level,continuous level and others explain in detail?

leamalaga03 said...

Hi

Tks very much for post:

I like it and hope that you continue posting.

Let me show other source that may be good for community.

Source: Transportation interview questions

Best rgs
David

dorababu said...

this questions are helpful for vlsi domain peoples..thanks for sharing the interview questions..
if you mention the all answers for each questions it will usefull for everyone.