How do I generate clock in Verilog ?

There are many ways to generate clock in Verilog; you could use one of the following methods:

Method #1

 1 initial begin

 2  clk = 0;

 3 end

 4    

 5 always begin

 6    #5  clk = ~clk;

 7 

 8 end

Method #2

 1 initial begin

 2   clk = 0;

 3   forever begin

 4      #5  clk = ~clk;

 5   end

 6 end

Method #3

 1 initial begin

 2   clk = 0;

 3 end

 4 

 5 always begin

 6    #5  clk = 0;

 7    #5  clk = 1;

 8 end

There are many ways to generate clocks: you may introduce jitter, change duty cycle.